JUNE 18–22, 2017

Presentation Details

Name: An Analysis of Core- & Chip-Level Architectural Features in Four Generations of Intel Server Processors
Time: Wednesday, June 21, 2017
02:15 pm - 02:45 pm
Room:   Analog 1+2
Messe Frankfurt
Speaker:   Johannes Hofmann, University of Erlangen-Nuremberg
Abstract:   This paper presents a survey of architectural features among four generations of Intel server processors (Sandy Bridge, Ivy Bridge, Haswell, and Broadwell) with a focus on performance with floating point workloads. Starting on the core level and going down the memory hierarchy we cover instruction throughput for floating-point instructions, L1 cache, address generation capabilities, core clock speed and its limitations, L2 and L3 cache bandwidth and latency, the impact of Cluster on Die (CoD) and cache snoop modes, and the Uncore clock speed. Using microbenchmarks we study the influence of these factors on code performance. This insight can then serve as input for analytic performance models. We show that the energy efficiency of the LINPACK and HPCG benchmarks can be improved considerably by tuning the Uncore clock speed without sacrificing performance, and that the Graph500 benchmark performance may profit from a suitable choice of cache snoop mode settings.