JUNE 18–22, 2017

Session Details

Name: Tutorial 12: Manycore Optimization Methods on Intel's 2nd Generation Xeon Phi (Knights Landing)
Time: Sunday, June 18, 2017
02:00 pm - 06:00 pm
Room:   Expose  
Breaks:04:00 pm - 04:30 pm Coffee Break
Presenter:   John Cazes, TACC
  Robert Evans, TACC
  Kent Milfeld, TACC
  Cyrus Proctor, TACC
Abstract:   As modern processors scale out (more cores and deeper vector units) rather than up (higher frequency), the importance of vectorization and multi-threading grows. This evolution towards manycore will require applications that are written to expose opportunities for vectorization and are designed to support multi-threaded execution. The Intel Knights Landing (KNL) processor is the next step in this manycore evolution. This tutorial will provide practical information and advice to enable experienced OpenMP and MPI programmers to enhance applications on the KNL. We’ll review the KNL’s architecture and discuss the impacts on performance of the different MCDRAM memory and cluster configurations. Recommendations regarding MPI and OpenMP task layout will discussed. We will focus on the use of reports and directives to guide optimization and implementation of efficient memory access and alignment. We also will showcase Intel VTune Amplifier XE’s and Advisor’s capabilities to provide detailed memory analysis and parallel code profiling. Optimization methods in multithreading will be covered in depth. This session will include hands-on exercises on the KNL-upgraded Stampede system at the Texas Advanced Computing Center.  

Content Level 
50% Intermediate 50% Advanced  

Targeted Audience 
This tutorial is intended for application developers who wish to optimize their codes to take advantage of manycore processors such as Intel’s Knights Landing.