JUNE 18–22, 2017

Session Details

Name: Experiences on Intel Knights Landing at the One-Year Mark
Time: Thursday, June 22, 2017
09:00 am - 06:00 pm
Room:   Platinum 2  
Breaks:11:00 am - 11:30 am Coffee Break
01:00 pm - 02:00 pm Lunch
04:00 pm - 04:30 pm Coffee Break
Organizer:   Richard Gerber, NERSC
  Michael A. Lysaght, ICHEC
  Simon J. Pennycook, Intel
  Estela Suarez, JSC
Speaker:   Wibe Albert de Jong, LBNL
Abstract:   The workshop will bring together software developers and technology experts to share challenges, experiences and best‐practice methods for the optimization of HPC workloads on Intel Xeon Phi (code-named Knights Landing, KNL). The workshop will cover application performance and scalability challenges at all levels, focusing on application tuning on large HPC systems with many KNL devices.The workshop will consist of three parts: a key-note, talks on the submitted papers, and a final panel session. The keynote will introduce the main features of current-generation Intel Xeon Phi processors -- including the various memory configurations and modes of operation available -- and provide a refresher on what’s public about future processor generations. The submitted talks shall cover optimization in real-world HPC applications, e.g. data layouts and code restructuring for efficient SIMD operation, thread management, use and performance comparison for different memory modes, etc. Papers describing application results on multi-node configurations and addressing KNL-specific features (e.g. use of MCDRAM) will be prioritized. The usability of tools for development, debugging and performance analysis will be covered. The panel session provides an opportunity to discuss optimization strategies for Intel Xeon Phi and to provide feedback to the toolchain developers.

Targeted Audience
Application developers on Intel Xeon Phi and other many-core platforms, experts in code optimization, decision makers for future system deployments. This workshop may have a companion BoF where a broader user discussion on performance tuning and optimization results is planned. 

For more details, please visit the workshop webpage at https://www.ixpug.org/events/workshop-isc17