|Name:||Strategies & Technologies for HPC after MOSFET Scaling Ends|
|Time:||Thursday, June 22, 2017
09:00 am - 06:00 pm
Frankfurt Marriott Hotel
|Breaks:||11:00 am - 11:30 am Coffee Break|
01:00 pm - 02:00 pm Lunch
04:00 pm - 04:30 pm Coffee Break
|Organizer:||George Michelogiannakis, LBNL|
|Jeffrey Vetter, ORNL & University of Tennessee-Knoxville|
|Speaker:||Karlheinz Meier, University of Heidelberg|
|Murray Thom, D-Wave Systems|
|Abstract:||The impending end of traditional MOSFET scaling has sparked research into preserving HPC performance improvements through alternative computational models. Currently, the community is tasked with enumerating and evaluating potential strategies to deal with this challenge. To better shape our strategy, we need to understand where each technology is headed and where it will be in a span of 20 years. Numerous issues become relevant in that timespan, such as inherent drawbacks, programmability, manufacturability, application domains covered, and many others. This workshop brings together experts who develop or use promising technologies to present the state of their work, and spark a discussion on the promise and detriments of each approach. This includes technologies that adhere to the traditional digital computational model, as well as new models such as neuromorphic and quantum computings. The workshop features presentations from selected papers, followed by a panel discussion to summarize and challenge the main arguments and findings of the workshop. This workshop also aims to attract experts from other fields in order to gain an understanding of potential future changes and impact to adjacent fields.
We aim to attract experts in technologies that are viable strategies for continued HPC performance scaling after MOSFETs stop scaling, as well as experts in related fields such as algorithms and runtimes who are interested in the future impact to their areas.
For more details, please visit the workshop webpage at http://workshops.postmoore.org/hcpn2017/